AMS IP VERIFICATION ENGINEER

About the Role

You will execute AMS IP integration and verification at the subsystem and full-SoC level. You will translate IP-level test cases into SoC environments, author SoC-level PDL test cases, execute regressions across RTL and gate levels, and utilize Tessent tools to secure comprehensive test coverage for mixed-signal designs.

Key Responsibilities

• Verify analog and mixed-signal IP integration across complex subsystem and SoC environments.
• Port IP-level test scenarios to SoC-level environments and author SoC-level PDL test cases.
• Run full regressions across RTL, Gate-Level Simulations (GLS), and Timing (SDF) environments.
• Execute Virtual Tester simulations and validate digital-analog boundaries.
• Implement test patterns using Siemens Tessent DFT tools, driving pattern generation and simulation sign-off.
• Bring up testbenches, integrate third-party IPs, and execute detailed waveform debugging.
• Generate EVCD and bench test collaterals to support silicon bring-up alongside ATE teams.

Required Qualifications & Skills

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or related technical field.
• 6 to 12 years of dedicated experience in AMS IP verification and SoC-level integration.
• Hands-on expertise with Siemens Tessent DFT tools for pattern generation and verification.
• Comprehensive functional knowledge of analog blocks: PLLs, FLLs, temperature/current/process sensors, and droop detectors.
• Proven experience in register configurability, interface verification, and PDL test development.
• Demonstrated capability in RTL, GLS, and timing simulation workflows.
• Scripting experience in Python, Perl, Tcl, or Skill.
• Active experience in silicon bring-up and ATE pattern diagnosis.