CPUSS DV ENGINEER / LEAD

Role Overview

We are looking for a CPUSS DV Engineer/Lead to drive verification of CPU and cache subsystems. This role covers everything from testbench development to CPU pipeline and coherence verification, and is suited to an engineer ready to own verification closure on complex CPU subsystems.

Key Responsibilities

• Develop SystemVerilog/UVM-based testbench environments for CPU and cache subsystems
• Develop and debug assembly-level tests for CPU validation
• Perform cache verification including memory consistency, CHI protocol, coherence manager, and shared L1/L2/L3 cache behavior
• Verify CPU pipeline units - Fetch, Decode, Schedule, and Execute stages
• Validate Load/Store unit functionality and vector datapath operations for correctness and performance
• Apply verification expertise on RISC-V architecture, including RVA23 standards
• Collaborate with cross-functional teams to debug RTL, testbenches, and simulations

Requirements & Qualifications

• 8-20 years of experience in CPU/SoC design verification
• Strong hands-on expertise in SystemVerilog and UVM
• Experience verifying CPU/cache subsystems and coherence protocols
• Working knowledge of RISC-V architecture and RVA23 standards
• Strong RTL debug and cross-team collaboration skills
• Prior experience leading or mentoring a verification team is a plus