DDR VERIFICATION ENGINEER

About the Role

You will lead functional verification for DDRPHY architectures and memory subsystems. You will own the full verification cycle from testplan creation to vector delivery, ensuring compliance with JEDEC standards and DFI specifications. You will collaborate closely with design teams to debug regression failures and resolve post-silicon bottlenecks.

Key Responsibilities

• Define comprehensive testplans, execute test sequences, and achieve 100% functional and code coverage closure.
• Verify DDRPHY controller logic and physical interface behaviors against strict timing parameters.
• Triage, debug, and resolve regression failure signatures at IP, subsystem, and SoC levels.
• Debug and root-cause complex hardware, software, and post-silicon issues in direct collaboration with design engineers.
• Deliver verification sign-off packages and complete technical documentation for memory subsystem releases.

Required Qualifications & Skills

• Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or Computer Engineering.
• 6 to 12 years of core verification experience focused on DDR and DDRPHY architectures.
• Mandatory: Proven, hands-on verification experience with LPDDR5 and LPDDR4 memory protocols.
• In-depth understanding of the DFI (DDR PHY Interface) protocol and JEDEC memory standards.
• Advanced expertise in Verilog, SystemVerilog, and UVM/OVM constrained-random verification environments.
• Strong analytical, root-cause analysis, and waveform debugging skills.
• Experience with bus protocols such as AMBA AXI and AHB.
• Post-silicon bring-up and hardware-software co-debug experience.
• Scripting proficiency in Perl or Python for automated regression suites.