DFT ENGINEER

Role Overview

We are looking for a senior DFT Engineer to drive design-for-test architecture and implementation for test chips, owning the flow from RTL insertion through pattern generation, simulation, and bring-up.

Key Responsibilities

• Drive DFT architecture and implementation across scan, MBIST, JTAG, and IJTAG (IEEE 1687) flows
• Perform DFT insertion at RTL and gate level, including LEC (pre- vs post-DFT and gate level)
• Implement DFT at both SoC and subsystem/block/partition level
• Drive SSN (Scan Streaming Network) implementation where applicable
• Own scan, MBIST, OCC, and EDT insertion using established DFT flows
• Generate, retarget, and simulate test patterns at block and SoC level
• Run zero-delay and SDF-based timing simulations
• Drive coverage closure and scan synthesis with timing constraint creation
• Support test chip bring-up using JTAG, scan, and MBIST-based patterns
• Develop SystemVerilog/UVM-based verification environments to validate DFT logic

Requirements & Qualifications

• 10+ years of experience in DFT engineering
• Strong hands-on expertise in scan, MBIST, ATPG, JTAG, and IJTAG flows
• Experience with industry-standard DFT tools (Tessent or equivalent), including SSN
• Proficiency in SystemVerilog/UVM-based verification environments
• Strong debug skills across gate-level simulations and pattern-based validation
• Experience taking DFT from RTL through test chip bring-up