DFX DV ENGINEER

Role Overview

We are looking for an experienced DFX DV Engineer to strengthen our design verification team. The role sits at the intersection of functional verification and design-for-test, and is well suited to an engineer who enjoys working across SoC/IP verification, silicon bring-up, and testability.

Key Responsibilities

• Develop and execute verification plans using SystemVerilog and UVM
• Perform functional verification of SoC and IP-level components
• Debug failures across simulation, emulation, and silicon
• Work closely with design and DFT teams to ensure testability and coverage
• Analyze and validate test patterns (ATPG/ATE)
• Support post-silicon validation and bring-up activities
• Collaborate with cross-functional teams to close verification gaps early in the design cycle

Requirements & Qualifications

• 8-20 years of experience in SoC/IP verification
• Strong hands-on expertise in SystemVerilog and UVM
• Solid understanding of SoC/IP verification methodologies
• Good debugging and problem-solving skills
• Working exposure to DFT concepts and testability requirements
• Experience supporting silicon bring-up and post-silicon validation is an advantage