E-FUSE MEMORY DESIGN ENGINEER

Role Overview

We are looking for a Memory Design Engineer with e-fuse / OTP memory experience to work on test chip design for one-time-programmable memory architectures, including shared-bias variants.

Key Responsibilities

• Design test chip circuits for e-fuse/OTP-based non-volatile memory architectures
• Develop memory design collateral for OTP and shared-bias variants
• Perform hands-on circuit design leveraging timing and power measurement fundamentals
• Run SPICE/simulation-based validation of memory design blocks
• Collaborate with layout and characterization teams to close test chip design
• Debug design issues identified during simulation and bring-up

Requirements & Qualifications

• 2-6 years of experience in memory design, with e-fuse/OTP memory experience strongly preferred
• Hands-on knowledge of basic timing and power measurement techniques
• Experience with SPICE/simulation tools
• Strong debugging and analytical skills