E-FUSE MEMORY LAYOUT ENGINEER

Role Overview

We are looking for a Memory Layout Engineer with e-fuse / OTP or SRAM layout experience to develop test chip layout for one-time-programmable memory architectures and support compiler-level layout closure.

Key Responsibilities

• Develop test chip layout for e-fuse/OTP-based non-volatile memory architectures, including shared-bias variants
• Design SRAM/memory leafcells and compiler-level layouts independently
• Run and close compiler-level LVS/DRC checks
• Support SRAM/memory layout compiler development
• Debug and resolve EM/IR issues on memory layouts
• Collaborate with design and characterization teams for layout signoff

Requirements & Qualifications

• 2-6 years of experience in memory layout, with e-fuse/OTP or SRAM layout experience preferred
• Ability to work independently on leafcell and compiler-level layout, LVS, and DRC
• Exposure to EM/IR fixing techniques
• Familiarity with layout tools such as Totem is a plus