FUNC PERF CORES VERIFICATION ENGINEER

About the Role

You will partner with SoC development teams to verify, simulate, and debug high-performance CPU cores (ARM, RISC-V), GPU, DSP, multimedia, peripheral, and high-speed IO blocks at RTL and gate levels. You will execute functional and performance coverage plans, build testbenches, and support silicon debug routines on bench and ATE setups.

Key Responsibilities

• Develop and maintain scalable DV environments for chip-level, cluster-level, and subsystem-level verification.
• Execute RTL verification, Gate-Level Simulations (GLS), and Timing (SDF) GLS using Cadence, Synopsys, or Siemens platforms.
• Verify complex subsystem functions including cache coherency, bus interconnects (NIC, NoC), and memory management units.
• Generate and convert ATE patterns, execute Virtual Tester simulations, and produce Bench CSV collaterals.
• Debug functional, AMS, and HSIO patterns on ATE and Bench setups to guarantee pattern stability across PVT corners.
• Root-cause coverage gaps and silicon defects in collaboration with architecture, design, and product engineering teams.

Required Qualifications & Skills

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or VLSI.
• 6 to 12 years of hands-on experience in SoC chip-level, cluster, or subsystem verification.
• In-depth understanding of microprocessor/microcontroller architecture, ARM or RISC-V core internals, and cache hierarchies.
• Command of standard SoC bus protocols: AXI, AHB, APB, and JTAG.
• High proficiency in Hardware Verification Languages (SystemVerilog) and methodologies (UVM, OVM).
• Practical familiarity with ATE formats and debug files: STIL, WGL, SVF, VCD, eVCD, and ATE fail datalogs.
• Scripting for automation using Python, Perl, Skill, or Tcl.
• Proven background in silicon debug and post-silicon validation.