HSIO PHY VERIFICATION ENGINEER

About the Role

You will verify High-Speed Input/Output (HSIO) PHY blocks at the IP, subsystem, and full-SoC level. You will build constrained-random verification environments, port physical-layer test cases into SoC environments, execute gate-level and timing regressions, and partner with product teams to validate high-speed transceivers during post-silicon bring-up.

Key Responsibilities

• Lead HSIO PHY integration verification across subsystem and full-SoC test environments.
• Port IP-level functional and PHY-layer test cases to the top-level SoC environment.
• Build and maintain SystemVerilog/UVM constrained-random testbenches and integrate third-party VIPs.
• Execute comprehensive regressions across RTL, Gate-Level Simulations (GLS), and back-annotated timing (SDF).
• Run Virtual Tester simulations to validate pattern compatibility with automated testing hardware.
• Generate EVCD and bench test collaterals for physical interface validation.
• Partner with ATE and laboratory teams to execute post-silicon bring-up and debug high-speed interface failures.

Required Qualifications & Skills

• Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or Computer Engineering.
• 6 to 12 years of hands-on experience in HSIO PHY and SoC-level verification.
• Comprehensive working knowledge of high-speed protocols and physical layers: USB2/3, PCIe, UFS, MIPI, or DDR PHY.
• Deep understanding of high-speed PHY functionality, including loopback modes, equalization, and calibration.
• Advanced expertise in SystemVerilog and UVM/OVM methodology.
• Strong waveform analysis, gate-level simulation debug, and timing verification skills.
• Experience with register interface configuration and controller-to-PHY co-verification.
• Automation and scripting skills in Python, Perl, Tcl, or Skill.
• Direct involvement in high-speed ATE pattern validation or lab bench characterization.