MEMORY LAYOUT ENGINEER

Role Overview

We are hiring a Memory Layout Engineer with 5–10 years of experience in SRAM, ROM, and custom layout at cell, array & peripheral levels (Immediate Joiners Only).

Key Responsibilities

• Apply deep memory layout expertise across SRAM, ROM, and related memory architectures
• Execute custom layout design for advanced memory at cell, array, and peripheral levels
• Work proficiently with Custom Compiler or Virtuoso, and ICV or Calibre for physical verification
• Ensure compliance with process rules, DRC/LVS checks, and memory design constraints across planar and FinFET nodes
• Perform RC extraction, parasitic reduction, and signal integrity (EMIR) analysis for reliable memory design

Requirements & Qualifications

• 5-10 years of experience in Memory Layout Design (SRAM, ROM)
• Hands-on expertise in Custom Layout at Cell, Array & Peripheral Levels
• Proficiency with Custom Compiler / Virtuoso
• Expertise in ICV / Calibre (DRC, LVS)
• Solid Planar & FinFET Node Process Knowledge
• Experience in RC Extraction, Parasitic Reduction & EMIR analysis
• Note: Immediate Joiners Only