PHYSICAL DESIGN ENGINEER (FCFP)

Role Overview

We are looking for an experienced Physical Design Engineer to own full-chip floorplanning and physical implementation, from RTL to GDSII, for complex SoC designs. This role combines strong implementation skills with exposure to full-chip signoff.

Key Responsibilities

• Own RTL-to-GDSII implementation for full-chip and block-level designs
• Handle synthesis, floorplanning, power planning, placement, CTS, routing, and timing closure
• Drive full-chip floorplanning decisions balancing timing, power, and area targets
• Coordinate with the physical verification team to close DRC/LVS signoff
• Support multi-patterning verification and fill strategies for advanced technology nodes
• Interface with the foundry on design rule clarifications and waiver approvals
• Develop and improve physical design automation and flow scripts

Requirements & Qualifications

• 8-20 years of experience in physical design and STA
• Strong hands-on expertise with physical design EDA tools (Cadence and Synopsys)
• Solid understanding of the RTL-to-GDSII flow, floorplanning, and timing closure
• Scripting proficiency in TCL and Shell
• Exposure to full-chip physical verification and signoff flows is an advantage