RTL Integration Engineer – PCIe Gen5+

Role Overview

We are looking for a highly experienced RTL Integration Engineer to lead PCIe Gen5 and next-generation controller and PHY integration for advanced SoC designs.

Key Responsibilities

• Integrate PCIe Gen5+ controllers and PHYs into complex SoC architectures
• Own end-to-end RTL integration including parameterization, clocking, reset, and CSR integration
• Ensure correct implementation of PCIe protocol layers (TL/DL/PHY) and LTSSM behavior
• Manage speed/width change, recovery, and reset scenarios across generations
• Drive PIPE PHY interface integration, including power-state and latency alignment
• Implement error handling, replay logic support, and AER reporting paths
• Optimize performance, latency, and power across multiple VCs and traffic classes
• Collaborate with DV, PHY, firmware, and software teams for compliance and bring-up readiness
• Support debug and silicon bring-up through visibility hooks and instrumentation

Requirements

• 8–12+ years of experience in high-speed interface RTL integration
• Silicon-proven PCIe Gen5+ experience (mandatory)
• Deep understanding of PCIe architecture (Root Complex, Endpoint, Switch)
• Expertise in LTSSM states, transitions, and recovery mechanisms
• Solid knowledge of TLP/DLLP formats, flow control, replay, and ordering rules
• Experience with PIPE interfaces and PHY interaction (rate/width change, power states)
• Multi-clock design, CDC, and reset sequencing skills
• Familiarity with ASPM (L0s, L1, L1.1, L1.2) and low-power integration
• Strong understanding of error handling, RAS, and AER capability integration
• Experience integrating PCIe into AXI/APB-based SoC fabrics

Preferred Qualifications

• Exposure to next-generation PCIe FLIT-mode architectures
• Experience with chiplet-based or multi-die SoC designs
• CXL awareness
• Post-silicon debug and bring-up experience