SCAN / MBIST DFT ENGINEER

About the Role

You will own Design-for-Test (DFT) activities for high-performance chip designs to enable efficient, high-coverage manufacturing test. You will architect scan-based logic tests, memory tests and repair, boundary scan, and high-speed interface testing. You will interface with front-end teams to integrate DFT features, coordinate with physical design teams on timing sign-off, and drive ATE pattern delivery for silicon bring-up.

Key Responsibilities

• Architect and implement complete DFT methodologies, including scan insertion, ATPG, MBIST, JTAG, and Scan Compression.
• Generate, simulate, and verify ATPG and compressed ATPG patterns using industry-standard EDA tools.
• Drive memory test and repair architectures, boundary scan implementations, and high-speed interface test setups.
• Interface with back-end physical design teams on timing constraints, clock design, and STA for test modes.
• Execute gate-level simulations (GLS) with back-annotated timing (SDF) across operational corners.
• Partner with Product and Test Engineering (PDTE) teams to deliver test vectors and troubleshoot silicon on Automated Test Equipment (ATE).
• Author comprehensive DFT architectural documentation and integration guidelines for front-end teams.

Required Qualifications & Skills

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or equivalent practical experience.
• 8 to 15 years of dedicated hands-on experience in DFT/DFD flows and methodologies.
• Demonstrated mastery of scan insertion, ATPG, MBIST, JTAG, Scan Compression, and at-speed testing.
• Strong working knowledge of IEEE standards: IEEE 1149.1, 1149.6, 1500, and 1687.
• Practical experience handling test data formats: BSDL, ICL, PDL, STIL, and CTL.
• Proven track record in silicon bring-up, pattern validation, and hardware debug on ATE platforms.
• Hands-on proficiency with industry-standard simulation and ATPG tool suites (Synopsys DFTMAX, Siemens Tessent, or Cadence).
• Automation and scripting capabilities in Python, Perl, or Tcl.
• Deep knowledge of silicon defect types, fault models, and low-power DFT architectures.