STANDARD CELL DESIGN ENGINEER

Role Overview

We are looking for an experienced Standard Cell Design Engineer to join our VLSI design team. The role involves designing, developing, and validating standard cell libraries for advanced technology nodes, with a strong focus on performance, power, and area optimization.

Key Responsibilities

• Design and develop standard cell circuits, including combinational, sequential, and special cells
• Perform transistor-level schematic design and simulation using industry-standard EDA tools
• Design and optimize power management kit cells such as level shifters, power gating, isolation, and always-on cells
• Characterize standard cells for timing, power, noise, and reliability across multiple PVT corners
• Perform PPA trade-off analysis across different cell topologies and architectures
• Support library development for advanced technology nodes (FinFET/CMOS)
• Collaborate with layout engineers on schematic, layout design, and circuit topology exploration
• Perform EM/IR, noise, and variation analysis
• Support physical design teams on timing closure and DRC/LVS fixes
• Debug silicon issues related to standard cell behavior

Requirements & Qualifications

• 3-7 years of experience in standard cell / custom circuit design and characterization
• Strong knowledge of CMOS fundamentals and transistor-level design
• Hands-on experience with tools such as Virtuoso, Spectre, HSPICE, or Liberate
• Understanding of STA, PVT corners, and reliability checks
• Basic understanding of standard cell layout concepts and DRC/LVS flows
• Exposure to advanced nodes (7nm/5nm/3nm) is a plus
• Scripting knowledge in Perl/Python/TCL preferred