STANDARD CELL LAYOUT ENGINEER

Role Overview

We are looking for a Standard Cell / Logic Layout Engineer with strong experience across advanced technology nodes to join our library development team, covering everything from logic cell layout to DRC/LVS signoff.

Key Responsibilities

• Layout design of logic standard cells (inverters, muxes, flops, complex logic gates) optimized for performance, area, and power
• Translate schematics into compact, DRC-clean layouts in collaboration with circuit designers
• Drive DRC and LVS closure using industry-standard tools (e.g., Calibre)
• Debug and resolve DRC, LVS, and physical signoff issues
• Handle cell abutment, profiling, and integration constraints
• Address layout-dependent effects (LDE) and multi-patterning/EUV compliance on advanced nodes
• Implement standard cell layouts on bulk CMOS and FinFET processes, including ESD, antenna, and EM handling
• Review and debug LEF, GDS, and abstract views for digital integration
• Automate layout QA, regression checks, and PDK-driven verifications using SKILL/Python/Perl/TCL
• Participate in library quality audits and signoff package preparation

Requirements & Qualifications

• 5+ years of custom layout experience in standard cell development
• Hands-on experience across advanced nodes (5nm/3nm/2nm FinFET or GAA) and/or bulk CMOS
• Strong proficiency in Cadence Virtuoso and Calibre
• Deep understanding of advanced DRC, LVS, and multi-patterning rules
• Strong scripting knowledge (Python/SKILL/Perl/TCL)
• Experience with version control and flow automation
• Good documentation and cross-team communication skills