Standard Cell Layout Engineer

Role Description

We are seeking a highly skilled and motivated Standard Cell Layout Engineer to join our network. In this role, you will be responsible for driving design, execution, verification, or alignment within key technical domains to deliver successful deliverables and high-calibre team outputs.

Key Responsibilities

• Perform custom physical layout design for standard cell libraries (combinational and sequential logic).
• Optimize leaf-cell architecture for density, cell-height constraints, and electromigration parameters.
• Debug and resolve complex DRC/LVS violations at the transistor level.

Qualifications & Requirements

• Proficiency using Cadence Virtuoso layout suites.
• Direct experience working with advanced sub-micron/FinFET process layers.