Find the role that moves your career forward.

You will own Design-for-Test (DFT) activities for high-performance chip designs to enable efficient, high-coverage manufacturing test. You will architect scan-based logic tests, memory tests and repair, boundary scan, and high-speed interface testing.

You will partner with SoC development teams to verify, simulate, and debug high-performance CPU cores (ARM, RISC-V), GPU, DSP, multimedia, peripheral, and high-speed IO blocks at RTL and gate levels.

You will execute AMS IP integration and verification at the subsystem and full-SoC level. You will translate IP-level test cases into SoC environments, author SoC-level PDL test cases, execute regressions across RTL and gate levels, and utilize Tessent tools.

You will lead functional verification for DDRPHY architectures and memory subsystems. You will own the full verification cycle from testplan creation to vector delivery, ensuring compliance with JEDEC standards and DFI specifications.

You will eliminate operational bottlenecks across ASIC and SoC design verification flows. You will architect, develop, and deploy software automation tools that accelerate chip design pipelines.

You will verify High-Speed Input/Output (HSIO) PHY blocks at the IP, subsystem, and full-SoC level. You will build constrained-random verification environments and port physical-layer test cases into SoC environments.

This role involves Functional and Performance verification using effective methodologies at Module/Subsystem/SoC/System level. A strong ability to map requirements into a traceable verification plan is essential. The ideal candidate will partner with local and global SoC and IP developers to drive best practices and continuous productivity improvement, with a "zero-defect" mindset.

We are looking for a highly experienced RTL Integration Engineer to lead PCIe Gen5 and next-generation controller and PHY integration for advanced SoC designs.

Seeking dedicated Operator Engineer Trainees (OET) for 50+ openings to operate and monitor production machinery, support daily manufacturing activities, and adhere to strict quality and safety standards in Chennai.

We are seeking an experienced AMS Verification Engineer to own mixed-signal verification from specification review through sign-off. Candidates must have strong hands-on experience in AMS Verification, Verilog-AMS, SystemVerilog, wreal Modeling, and Xcelium AMS / VCS AMS.